entity full_adder_3bit_12bit is
Port ( a : in STD_LOGIC_VECTOR (11 downto 0);
b : in STD_LOGIC_VECTOR (11 downto 0);
c : in STD_LOGIC_VECTOR (11 downto 0);
c_in : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (11 downto 0);
c_out : out STD_LOGIC);
end full_adder_3bit_12bit;
architecture Behavioral of full_adder_3bit_12bit is
component full_adder
port
(
a, b, c_in: in std_logic;
sum, c_out: out std_logic
);
end component;
signal carry1 : std_logic_vector(11 downto 0);
signal carry2 : std_logic_vector(11 downto 0);
signal sum_temp: std_logic_vector(11 downto 0);
begin
FA1: full_adder port map(a(0), b(0), c_in, sum_temp(0), carry1(0));
FA2: full_adder port map(a(1), b(1), carry1(0), sum_temp(1), carry1(1));
FA3: full_adder port map(a(2), b(2), carry1(1), sum_temp(2), carry1(2));
FA4: full_adder port map(a(3), b(3), carry1(2), sum_temp(3), carry1(3));
FA5: full_adder port map(a(4), b(4), carry1(3), sum_temp(4), carry1(4));
FA6: full_adder port map(a(5), b(5), carry1(4), sum_temp(5), carry1(5));
FA7: full_adder port map(a(6), b(6), carry1(5), sum_temp(6), carry1(6));
FA8: full_adder port map(a(7), b(7), carry1(6), sum_temp(7), carry1(7));
FA9: full_adder port map(a(8), b(8), carry1(7), sum_temp(8), carry1(8));
FA10: full_adder port map(a(9), b(9), carry1(8), sum_temp(9), carry1(9));
FA11: full_adder port map(a(10), b(10), carry1(9), sum_temp(10), carry1(10));
FA12: full_adder port map(a(11), b(11), carry1(10), sum_temp(11), carry1(11));
FA13: full_adder port map(sum_temp(0), c(0), '0', sum(0), carry2(0));
FA14: full_adder port map(sum_temp(1), c(1), carry2(0), sum(1), carry2(1));
FA15: full_adder port map(sum_temp(2), c(2), carry2(1), sum(2), carry2(2));
FA16: full_adder port map(sum_temp(3), c(3), carry2(2), sum(3), carry2(3));
FA17: full_adder port map(sum_temp(4), c(4), carry2(3), sum(4), carry2(4));
FA18: full_adder port map(sum_temp(5), c(5), carry2(4), sum(5), carry2(5));
FA19: full_adder port map(sum_temp(6), c(6), carry2(5), sum(6), carry2(6));
FA20: full_adder port map(sum_temp(7), c(7), carry2(6), sum(7), carry2(7));
FA21: full_adder port map(sum_temp(8), c(8), carry2(7), sum(8), carry2(8));
FA22: full_adder port map(sum_temp(9), c(9), carry2(8), sum(9), carry2(9));
FA23: full_adder port map(sum_temp(10), c(10), carry2(9), sum(10), carry2(10));
FA24: full_adder port map(sum_temp(11), c(11), carry2(10), sum(11), carry2(11));
c_out <= (a(11) and b(11)) xor (a(11) and c(11)) xor (b(11) and c(11));
end Behavioral;