FSM that series in date with X frequency and serious out data with 2X frequency

[39123811]

FSM that series-in data with X frequency and series-out data with 2X frequency

There is a topic about clock domain crossing and if two register with two different clock, some data might miss during transition due to set up time violation.

Most of time a FIFO can solve this problem.

But my question is can I design a FSM to solve this.

Circuit description for both VHDL and Verilog is OK, I just wanna figure out how does the logic inside this kind of FSM work. If you need more details to figure this out please let me know.

Thanks

The original information source is :

if the input sequence is "00101111", then the output in the destination domain will be "0011". Here the third data value in the input sequence which is "1" is lost

Solution. In order to prevent data loss, the data should be held constant in the source domain long enough to be properly captured in the destination domain. In other words, after every transition on source data, at least one destination clock edge should arrive where there is no setup or hold violation so that the source data is captured properly in the destination domain. There are several techniques to ensure this.
For example, a finite state machine (FSM) can be used to generate source data at a rate, such that it is stable for at least 1 complete cycle of the destination clock. This can be generally useful for synchronous clocks when their frequencies are known.

 

[barry]

Just holding data 'long enough' is not good enough for asynchronous clock domains. You still have to meet setup and hold times in the receiving domain, and just because the data was stable for a long time(many receiver clock cycles) is no guarantee that it won't change too close to the receiving clock edge. You will still need to use a synchronizer on the receiving end.

 

[mrflibble]

You start by defining the problem more precise. Different frequency ==> can be anything. What you show is just a very small subset of possible "different frequency" scenarios. In fact, a x2 frequency with edges nicely aligned as you show ... luxury problem. XD

So what is the exact clock relationship? And any datarate restrictions?

 

[39123811]

You start by defining the problem more precise. Different frequency ==> can be anything. What you show is just a very small subset of possible "different frequency" scenarios. In fact, a x2 frequency with edges nicely aligned as you show ... luxury problem. XD

So what is the exact clock relationship? And any datarate restrictions?

If the phase and freq relationship just like shown on figure above? Is it possible to fix data missing problem from source to destination reg by building a FSM?

 

[mrflibble]

What do I know? Define problem. Get answer. *beep* *boop*


Of course you can solve it (with or withouh FSM) if you define what constitutes solved. For the "missed data bit" what do you define as the correct answer? For you current example it could be either 1 or 0, depending on your requirements... Nothing magic about it, but you will have to choose which part of the waveform is valid.

 

[39123811]

What do I know? Define problem. Get answer. *beep* *boop*


Of course you can solve it (with or withouh FSM) if you define what constitutes solved. For the "missed data bit" what do you define as the correct answer? For you current example it could be either 1 or 0, depending on your requirements... Nothing magic about it, but you will have to choose which part of the waveform is valid.

My apologize~

OK I will describe question very detail step by step.

The problem is related to clock domain crossing, assume the circuit is given below:

Since C1 and C2 are two different clock, now assume the relationship of C1 and C2 are same phase but different frequency(interger 2), only focus on this case I know there are many other possibilities due to phase and freq relationship.

Since data is transfer from a faster clock to a slower clock, there might be data transfer loss, an example is given below,

In this case, the input sequence is "00101111", then the output in the destination domain will be "0011". Here the third data value in the input sequence which is "1" is lost .
There would be another extreme case, assume input sequence is "01010101", the destination domain would cover two input data in its clock cycle HOWEVER only later data would be caught.

What I want is just series in and series out. what is input sequence and would be series out with the same one. Like 01010101->input, output->01010101.
My question is that is it possible to build a FSM between different clock domain reg to solve this question to avoid data loss ?

Thanks a lot

 

[barry]

You are really getting your brain tied in knots. Simply, there is NO WAY to sample a data stream with a clock slower than the data rate. You will need to use some kind of storage element (FIFO, etc.). The question of a FSM is irrelevant; yes, you can use a FSM to control your FIFO, but you are going to need SOME KIND OF STORAGE. And your FSM is going to have to use your source clock.

 

[mrflibble]

That's a very detailed description of exactly the same thing as before.

Yes in this case you can define something that takes care of it and no there is no magic bullet.

You could for example extend that 10 to effectively be 11, so that the slow clock domain always samples a stable 1. But this begs the question what are you trying to do? As Barry points out you cannot just stuff in a high datarate signal into a lower clock and hope everything is going to be fine. If you have clearly defined situation like ... 111011 in the fast clock domain should arrive as 111 in the slow clock domain then you can do that. No FSM required, although one could argue that anything with a FF in it and new output depending on an input and previous output is an FSM.

Soooo why exactly do you want to do this? Because if I ask what I'll get an even more detailed description of same. XD So better ask why.

Stupid question: what is the data rate supposed to be on either side? Data rate, not clock rate.

 

[39123811]

You are really getting your brain tied in knots. Simply, there is NO WAY to sample a data stream with a clock slower than the data rate. You will need to use some kind of storage element (FIFO, etc.). The question of a FSM is irrelevant; yes, you can use a FSM to control your FIFO, but you are going to need SOME KIND OF STORAGE. And your FSM is going to have to use your source clock.

Thanks a lot. That is the answer I am looking for.

Can you give me some clue about how to use a FSM to control FIFO enable to avoid data loss in the above situation?

 

[mrflibble]

Can you give me some clue about how to use a FSM to control FIFO enable to avoid data loss in the above situation?

Past me tried to make a bet with future me that you were going to ask that in the near future. "Want to bet he's going to ask that?" I asked. "Noooooooo" I said, "I remember our last bet."

Too bad really, I would have won EUR 10. :|

 

[39123811]

Past me tried to make a bet with future me that you were going to ask that in the near future. "Want to bet he's going to ask that?" I asked. "Noooooooo" I said, "I remember our last bet."

Too bad really, I would have won EUR 10. :|

I reply him just because he answer straightforward and I am working when I check my post here. And I want to give you a reply after a fully consideration. That's is why I don't answer you on time. Could you please give me more time to reply you that? I don't have any negative meaning by doing that just he reply me first and what he answered makes me can reply just take a glance.

If what I did make you frustrated, I apologize for that.

 

[mrflibble]

Heh, no worries. I just thought it funny you asked that, because I was pretty much waiting for it. XD

Barry's key point is: "The question of a FSM is irrelevant"

You seem to be hung up on an FSM being a magic way to solve this. You can solve it with a FF + a bit of logic. The main point you seem to be missing is .... oh I don't know how to express it differently. See previous messages really. I'll just wait for barry to explain it and then I can learn something to improve my communication skills. Improvement allround! yay!

 

[barry]

simple answer: Use the vendor's drop-in dual-clock FIFO. Your source clock drives the write port, your receive clock drives the read port. DONE! You don't have to worry about those pesky timing issues because somebody smarter than us already did (presumably).

I'm still confused about what you really want. Do you want to know HOW a FIFO works, or are you looking for a particular solution to a particular problem?

 

[39123811]

simple answer: Use the vendor's drop-in dual-clock FIFO. Your source clock drives the write port, your receive clock drives the read port. DONE! You don't have to worry about those pesky timing issues because somebody smarter than us already did (presumably).

I'm still confused about what you really want. Do you want to know HOW a FIFO works, or are you looking for a particular solution to a particular problem?

barry thanks for your patient for answering this question.

I know a FIFO can solve this question since it is a data transfer through clock domain boundaries.

The reason I ask this is I read a reference about different clock domain, the related website is :

**broken link removed**

When the paper goes to a particular situation for clock phase relation just like I mention above, The paper write following words:
"For example, a finite state machine (FSM) can be used to generate source data at a rate, such that it is stable for at least 1 complete cycle of the destination clock. This can be generally useful for synchronous clocks when their frequencies are known."

That's why I am confused, can a FSM solve this issue, and how? If I miss some information could you track above sentence on the website I give to you?

Now it seems it is impossible and author has a magic power to solve this issue with JUST A FSM.

 

[rberek]

This article is a bit odd...

It is describing a serial data stream generated by a 2x clock and received by a 1X clock, with the clocks being in phase.

The first example shows the the data sequence 00110011 being sent by the faster clock domain to the slower clock domain. The slower clock domain will capture 0101. The article states that this means data was not lost. That is a matter of opinion! If you were meaning to send 'h33 and got 'h5, then you'd be p**sed off. If you were sending 'h3 by stretching the length of the four bits to be each one slow-clock period wide, then you'd be happy. I think this is what they were trying to describe.

But in the next example, they send 'h2F and show it being corrupted since two of the bits change too fast to be seen by the slow clock. Of course this is corrupted in this case.

The mention of an FSM only applies to the special case where you have complete control over the source and destination blocks and freedom to throttle data. For example, flag bits that are sent across clock domains in rate-adapt FIFOs. The faster domain is free to make the flag 2+ destination clocks long. Or if you are also designing the serial data generator, you are free to make the data slow enough to be sampled. But even in any event, no FSM is required to lengthen simple data signals - just a few flip flops in series and some OR gates will make a pulse stretcher.

For the general case in going from fast to slow, as has been mentioned, a rate-adapt (clock crossing) FIFO would be used. This assumes the FIFO can back-pressure the data source or the fast data arrives in bursts that will not overflow the FIFO.

Again, the description they give is not one I would have used.

r.b.

 

[barry]

The key here is that the article (as r.b. said more politely than I) is basically useless. IF AND ONLY IF you've got two synchronous(important!!) clocks and IF AND ONLY IF you output the data from the fast domain at the rate of the slow domain THEN a FSM would work with no storage elements. Big deal. This is a trivial case.

For the more general cases of non-synchronous clocks, or fast data into a slower domain, you need to forget about your FSMs and worry about the other issues.

I'm softening my stance on the article. It actually says "For example, a finite state machine (FSM) can be used to generate source data at a rate, such that it is stable for at least 1 complete cycle of the destination clock. This can be generally useful for synchronous clocks when their frequencies are known. For asynchronous clock domain crossings, techniques like handshake and FIFO are more suitable."

You seem to have latched onto the "FSM" statement and ignored everything else.

 

[39123811]

This article is a bit odd...

It is describing a serial data stream generated by a 2x clock and received by a 1X clock, with the clocks being in phase.

The first example shows the the data sequence 00110011 being sent by the faster clock domain to the slower clock domain. The slower clock domain will capture 0101. The article states that this means data was not lost. That is a matter of opinion! If you were meaning to send 'h33 and got 'h5, then you'd be p**sed off. If you were sending 'h3 by stretching the length of the four bits to be each one slow-clock period wide, then you'd be happy. I think this is what they were trying to describe.

But in the next example, they send 'h2F and show it being corrupted since two of the bits change too fast to be seen by the slow clock. Of course this is corrupted in this case.

The mention of an FSM only applies to the special case where you have complete control over the source and destination blocks and freedom to throttle data. For example, flag bits that are sent across clock domains in rate-adapt FIFOs. The faster domain is free to make the flag 2+ destination clocks long. Or if you are also designing the serial data generator, you are free to make the data slow enough to be sampled. But even in any event, no FSM is required to lengthen simple data signals - just a few flip flops in series and some OR gates will make a pulse stretcher.

For the general case in going from fast to slow, as has been mentioned, a rate-adapt (clock crossing) FIFO would be used. This assumes the FIFO can back-pressure the data source or the fast data arrives in bursts that will not overflow the FIFO.

Again, the description they give is not one I would have used.

r.b.

The key here is that the article (as r.b. said more politely than I) is basically useless. IF AND ONLY IF you've got two synchronous(important!!) clocks and IF AND ONLY IF you output the data from the fast domain at the rate of the slow domain THEN a FSM would work with no storage elements. Big deal. This is a trivial case.

For the more general cases of non-synchronous clocks, or fast data into a slower domain, you need to forget about your FSMs and worry about the other issues.

I'm softening my stance on the article. It actually says "For example, a finite state machine (FSM) can be used to generate source data at a rate, such that it is stable for at least 1 complete cycle of the destination clock. This can be generally useful for synchronous clocks when their frequencies are known. For asynchronous clock domain crossings, techniques like handshake and FIFO are more suitable."

You seem to have latched onto the "FSM" statement and ignored everything else.

Thanks for your detail explanation ! Sorry to reply late, just back from a long working trip.

I know what I ask is not practical and we can not estimate the two clock phase relationship if signal go across two different domain thus FIFO would be the best solution for multiple-data transport.

OK I admit what I am going to ask is just for theory analysis purpose and might not be practical at all.

Just like you said: IF AND ONLY IF you've got two synchronous(important!!) clocks and IF AND ONLY IF you output the data from the fast domain at the rate of the slow domain THEN a FSM would work with no storage elements.

Can you tell me how to design such a FSM to buffer data from fast clock to slow clock? Since there is no storage element like FIFO used in this case how can FSM handle such a particular case without data losing?

Just like you mentioned, I doubt the article when the author introduce FSM for this special case. I have no idea how to build such a FSM. Or I have some misunderstanding about the true meaning of data loss in this case with author.

If this can be figured out I will ask such kind of question for the person who I give an interview.

 

[barry]

You're going to ask this as a question in an interview????? You don't even understand it yourself, and you're going to ask somebody else to explain it? Pardon me, but I've got better things to do than to help you contrive stupid questions in an attempt to trip up people you are interviewing. I would certainly not want to work for someone who operates like this.

 

[BradtheRad]

This is similar to baud rate in modem communications. It is up to the receiving computer to detect the time period of a bit, and to keep up with data at the moment it comes in.

Or a morse code copyist. If he cannot keep up, he will drop letters.
Unless he stores the transmission by recording it, then plays it back at a slower speed.

 

[39123811]

You're going to ask this as a question in an interview????? You don't even understand it yourself, and you're going to ask somebody else to explain it? Pardon me, but I've got better things to do than to help you contrive stupid questions in an attempt to trip up people you are interviewing. I would certainly not want to work for someone who operates like this.

If that makes you make I am sorry about that. The reason I mention is I ask people around me and no people have any idea, that's why come out a idea with what you are angry. Please don't make too serous about that just is a joking and assume this can be figured out.

Nevertheless, thanks anyway.