-- FSM states
type state is (idle, init, init_shift, subtract, test, operation_sub1, operation_sub0, correction, finished);
signal current_state, next_state : state;
begin
-- FSM
control: process(current_state, start, S_in, counted)
begin
-- Default signals
en_M <= '0';
en_Q <= '0';
en_A <= '0';
en_C <= '0';
en_S <= '0';
reset_reg <= '1';
shift <= '0';
stop <= '0';
start_out <= '0';
sub <= '0';
next_state <= idle;
-- Switch/case states
case current_state is
when idle =>
reset_reg <= '0';
if start='1' then
next_state <= init;
else
next_state <= idle;
end if;
when init =>
en_A <= '1';
en_Q <= '1';
en_M <= '1';
start_out <= '1'
next_state <= init_shift;
when init_shift =>
en_Q <= '1';
en_A <= '1';
en_S <= '1';
shift <= '1';
next_state <= subtract;
when subtract =>
en_A <= '1';
en_M <= '1';
en_S <= '1';
sub <= '1';
next_state <= test;
-- HERE BEGINS MY DOUBT
when test =>
en_Q <= '1';
shift <= '1';
en_C <= '1';
if counted=N/2-1 then
if S_in='0' then
sub <= '1';
next_state <= finished;
else
next_state <= correction;
end if;
else
-- Shift di A (e S)
en_A <= '1';
en_S <= '1';
if S_in='0' then
sub <= '1';
next_state <= operation_sub1;
else
next_state <= operation_sub0;
end if;
end if;
--
when operation_sub1 =>
-- Sottrazione SA=SA-M
en_A <= '1';
en_M <= '1';
en_S <= '1';
sub <= '1';
next_state <= test;
when operation_sub0 =>
-- Addizione SA=SA+M
en_A <= '1';
en_M <= '1';
en_S <= '1';
next_state <= test;
[...]
end case;
end process;
-- Update FSM states
update: process(clk_in, next_state, reset)
begin
if reset='0' then
current_state <= idle;
elsif rising_edge(clk_in) then
current_state <= next_state;
end if;
end process;