jasmine123
Newbie level 5
I have tried to replace the while with a FSM model. But not successful in doing so. The output which is k is not passed to the output port.
Code:
1: while T[16] = 1 do // if (MSB bit of T==1)
2: T[16] = 0 //set the MSB bit to 0
3: T = T + (2**16 mod Y ) //and a precomputed value and if MSB bit is again 1 then repeat from line 8
return T
Code:
module fsm_model(clk,t,r,k);
input clk;
input [16:0] t;
input [16:0] r;
output reg [16:0] k;
reg state;
reg [16:0] g;
reg [16:0] h;
always @ (posedge clk)
begin
h = t;
state = h[16];
case (state)
1'b0:
begin
k = {1'b0,h[15:0]};
state = 0;
end
1'b1:
begin
g = {1'b0,h[15:0]};
h = g[16:0]+ r[16:0];
if (h[16:0] > 16'hFFFF)
state = 1'b1;
else
state = 1'b0;
end
endcase
end
endmodule