FSM for 4-bit parallel adder/subtractor in verilog

[abanah]

Can anyone plz help me out in creating fsm for 4-bit parallel adder/subtractor circuit..

 

[TrickyDicky]

Im sure we can. Post what you have so far and post what errors you've got ajnd we'll help

 

[sweet2shine]

can any one post 16 bit reversible alu using reversible logic gates

- - - Updated - - -

can u help me in reversible alu using logic gates

 

[TrickyDicky]

what is reverible ALU and what are reversible logic gates?

 

[mrflibble]

can u help me in reversible alu using logic gates

Google on "ALU Toffoli gates", that should get you started. So now you can get started.

 

[abanah]

Im sure we can. Post what you have so far and post what errors you've got ajnd we'll help

Created fsm for full adder alone.. Is it possible to call fsm of full adder inside that of fsm for parallel adder/subtractor??

module fsm_fa(data,su1,rst,clk,sum1,e1);
input clk,rst;
input [1:0]su1;
input [2:0]data;
output reg [1:0]sum1;
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4,s5=3'd5,s6=3'd6,s7=3'd7;
reg [2:0]ps,ns;
output reg e1;
reg sum,carry;

always@(posedge clk or negedge rst)
begin
if(rst==1'b0)
ps<=s0;
else
ps<=ns;
end

always@(ps,data)
begin

case(data)

s0: begin
sum<=0;
carry<=0;
ns<=s1;
end

s1: begin
sum<=1;
carry<=0;
ns<=s2;
end

s2: begin
sum<=1;
carry<=0;
ns<=s3;
end

s3:  begin
sum<=0;
carry<=1;
ns<=s4;
end	

s4:  begin
sum<=1;
carry<=0;
ns<=s5;
end

s5:  begin
sum<=0;
carry<=1;
ns<=s6;
end

s6:  begin
sum<=0;
carry<=1;
ns<=s7;
end

s7:  begin
sum<=1;
carry<=1;
ns<=s0;
end

endcase
sum1<={sum,carry};

end

always@(sum1,su1)
begin
  if(sum1==su1)
    e1=0;
    else
      e1=1;
 end
endmodule

The above program indicates the online checker for full adder.. In the same way i have to create online checker for the 4bit parallel adder/subtractor part using fsm.. Can u plz help me out..
Thank u in advance.