I want to programme a FSM (finite state machine) and the only problem left is, that I have to distinguish a certain bit pattern. How can I do this in VHDL? I only want to distinguish the first bit and in the next step the following 5 bits (in 2 steps)
For example:
My register holds 011010
first step: distinguish MSB (0 or 1)
second step: distinguish second bit to LSB
the bit pattern is transmitted over the serial IF (pc to fpga board) with a baud rate of 38900! Do you know smthg in VHDL where I can distinguish my input like this:
Hi
if your baud rate is 38900 so your frequency is 20 KHz. so if you are working in async mode your line must be high and when want to transfer data one start bit and 8 bit data and one stopbit follow it. you shold work with frequency equal to 16 multply by data rate that is frequency 320 KHz. you should start to check your line to see if it is changed to zero then start to sample it till middle of bit and if it is low for more number of samples write zero to your registers and so for other bits. if you are working sync mode you should start to sample and save data to read to your desired sequence.