modulesimple (Clock, Resetn, w, z);input Clock, Resetn, w;
outputz;reg[2:1] y;parameter[2:1] A =2’b00, B =2’b01, C =2’b10;// Define the sequential blockalways@(negedgeResetn orposedgeClock)beginif(Resetn ==0) y<=A;elsecase(y)
A:if(w) y<=B;else y<=A;
B:if(w) y<=C;else y<=A;
C:if(w) y<=C;else y<=A;default:y<=2’bxx;endcase// z=(y==c); output at this is one clock cycle after y changes to c,z here is regend// Define output
assignz=(y==C);output at this becomes one at same time as y changes to c
endmodule
hi arya
first assignment is in always block and that's and u have used non blocking state ment that's why it is updating after one clock.. if u see synthesis it will come out from a flop
and one is continuous statement hence it will update as the transaction is done if u synthesis rtl it will be from combinational circuit..