Hello master_picengineer,
After you completed the RTL coding and synthesis,
the synthesized netlist ( *.v ) will be passed to backend to do floorplanning and clock trunk/CTS.
the constraint and library used in synthesis ( *.sdc, *.lib, *.db ) will be passed to backend to do STA.
From analog design ( IO + standard cell ),
they will pass the IO and standard cell physical information ( *.lef ) for floorplanning, placement and routing.
they will also pass the IO and standard cell full physical information ( *.gds ) for
DRC, LVS verification.