From Java code to Verilog?

[membersound]

Hi,

hope I chose the right forum for my topic:
I'm trying to write a small java program that is capable of producing Verilog code. As I hardly know the Verilog language, I have problems creating a simple example.

Let's assume we have 2 inputs a, b, and 1 output c. Also 2 states. State1 is the initial state, and goes to State2 for a certain condition wire1, which requires b = 1.
My output in this example would have state2 & a as condition to be met.

Question: Using the approximate design below, how would the full Verilog code look according to my example?

//simplified without inheritance
class Input {
    String varname;
    new Input(String varname);
}

class Output {
    String varname;
    String condition;
    new Output(String varname, String condition);
}

class State {
    String varname;
    new State(String varname);
}

class Wire {
    String condition;
    Input input;
    Ouput output;
    new Wire(Input input, Output output, String condition);
}

Input input1 = new Input("a");
Input input2 = new Input("b");
State state1 = new State("initial");
State state2 = new State("following");
Wire wire12 = new Wire(state1, state2, "b");
Ouput output1 = new Output(c, "state2 & a");

How would the verilog code have to look based on this?

module BasicFsm(
    input clock,
    input reset,
    input a,
    input b,
    output c
);

always @(posedge clock)
//how to continue here?

Thanks for any help.