Frequency of operation in state machines

[ukapil]

I have two programs. One has a state machine of 24 states while the other has 5 state machines of 5 states each. The functionality of both the programs is same. Which one will give me a higher frequency of operation ?
Is there any limitation in state machines dues to which the frequency of operation reduces ?

The device i am targetting is Virtex4LX60 & my frequency requirement is 275 Mhz.
Presently i am just getting a Fmax of 200 Mhz. Any suggestions/advice on improving the frequency are welcome !

 

[Ace-X]

State Machines.

I would suggest to use Block RAM to implement state-machine (if your FSM have average complexity to be implemented as ROM). It will give you the highest possible frequency, ability to share 2 ports of Block RAM as 2 independent FSM with the same structure, and the flexibility to dynamiclly change FSM behaviour just by writing new content to Block RAM.

 

[sp]

Re: State Machines.

I have two programs. One has a state machine of 24 states while the other has 5 state machines of 5 states each.

could some1 explain to me how to implement the 5 state machines wth 5 states each..how to connect this 5 state machines together in VHDL....

to be more clear...if we r in 1 state machine n when we reach a state in this machine where we would like to proceed to another state machine...is it posible...could someone try explain to me to clear my doubt....

im quite new in VHDL...thanxs in advance...

sp

 

[ukapil]

Re: State Machines.

Its simple to use 5 FSMs in VHDL. Make a signal high after the first FSM gets over. Trigger the second FSM on this signal & so on..

 

[Renjith]

Re: State Machines.

The device i am targetting is Virtex4LX60 & my frequency requirement is 275 Mhz.
Presently i am just getting a Fmax of 200 Mhz. Any suggestions/advice on improving the frequency are welcome !

have u checked ur timing report?
whether ur critical path contains too much of logic or routing delays?

to improve performance, u can do some few things like
signal duplication( to reduce the fanout),
here u tell ur tool to keep the redundant logic.
pipelining is another good option for improving the clock in ur design.

xilinx tools(timing Analyzer) infact guides you do improve ur design depending on the type of delay in ur critical path.

 

[Black Jack]

Re: State Machines.

I have two programs. One has a state machine of 24 states while the other has 5 state machines of 5 states each. The functionality of both the programs is same. Which one will give me a higher frequency of operation ?
Is there any limitation in state machines dues to which the frequency of operation reduces ?

The device i am targetting is Virtex4LX60 & my frequency requirement is 275 Mhz.
Presently i am just getting a Fmax of 200 Mhz. Any suggestions/advice on improving the frequency are welcome !

I think that design with one FSM more reliable then with 5.
For 24-state FSM we have 8 illegal states, for 5 FSM with 5 states 15 (its optimistic)
and you must know how to make transition to known state for all combination
of five 5-state FSM.

 

[phoenixfeng]

State Machines.

i think the synthesis tool is also import
different tool produce different result
i had synthesised a 8 state machine in synplify, leonardospectrum,and XST,they each produce different result, from my opinion, when you coding, think about the support of synthesis tool,and see the reference manual of the tool you'll learn more

 

[Hero]

Re: State Machines.

Hi,

You first need to consider both solutions at Boole level and compare number of P-terms in both cases.

If you use high P-term macro-cells for state machine implementation number of P-terms is not so relevant. In that case you need to compare number of occupied macro-cells for both solutions.

Also you can transform original state machine to some functional equivalent to reduce number of P-terms.

Use don't care states for unused states in state machine to improve optimization and to reduce number of P-terms.

During synthesis process use optimization for speed and compare both solutions.

Try sythesis with different coding values for states (e.g. STATE0=1, STATE1=4, STATE2=3, ... ) and check results. Sometimes you can find optimal solution with these tricks.

 

[zape]

State Machines.

First of all you must constraint your clock for your synthesis tool and then configure the synthesis tool for optimization in speed and select one-hot encoding as FSM encoding algorithm.
If this do not work you should have to review your hdl.

 

[fpga_man]

Re: State Machines.

Are you sure of the good quality of your vhdl code? odes the xilinx synthesis tool recognize a state machine?
If not, rewrite the vhdl.

If yes, then you must find the critical path! to understand where the combinatory part has to be changed! this with timing analysis

You can also try to change the coding of the SM. (one hot, bianry, two hot...)
Normally the one hot is often the fastest. this is declared in vhdl code (attributes...), or in synthesis options

you must also put a timing constraint to improove the PAR...

 

[nemolee]

Re: State Machines.

I would suggest to use Block RAM to implement state-machine (if your FSM have average complexity to be implemented as ROM). It will give you the highest possible frequency, ability to share 2 ports of Block RAM as 2 independent FSM with the same structure, and the flexibility to dynamiclly change FSM behaviour just by writing new content to Block RAM.

Can you explain more detail? Or you can provide one example file for our reference. Thanks.

 

[Ace-X]

Re: State Machines.

I would suggest to use Block RAM to implement state-machine (if your FSM have average complexity to be implemented as ROM). It will give you the highest possible frequency, ability to share 2 ports of Block RAM as 2 independent FSM with the same structure, and the flexibility to dynamiclly change FSM behaviour just by writing new content to Block RAM.

Can you explain more detail? Or you can provide one example file for our reference. Thanks.

Here is short description in relation to ROM-based implementation. It is the same, but in BlockRAM case you already have registered outputs.

The state is stored in an external register whose outputs are fed back as addresses to the ROM.
The FSM has n inputs, k outputs, and m state bits. The n+m input bits and next-state bits form the ROM's address lines. The k+m output and state bits form the ROM's output lines. Thus, we need a ROM of 2^(n+m) words of k+m bits each to implement FSM.

 

[jnanabindu]

Re: State Machines.

I think that using 5 state machines will give a higher speed of operation compared the other alternative. However, one needs to be careful while coding 5 state machines. But, if you want higher speeds, the implementation of state machine on BRAM is the other alternative.