Frequency Divider with VHDL

[ahmed saeed]

Hi,
I'm trying to write a VHDL code for frequency counter count 2 seconds ,I using Altera board DE2 frequency 27 MHz. I need a 2second count as the output of clock divider.
I write the code but I'm not sure if is right or mot so please Can you verify and correct my code?

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity two_sec_cnt is
Port (
clk : in std_logic;
enl : in std_logic;
second : out std_logic
);
end two_sec_cnt;

architecture Timer of two_sec_cnt is
constant max_count : natural := 54000000;
-- I used 27MHz clock
begin
process (clk, enl)
variable count : natural range 0 to max_count;
begin
if (enl = '0') then
count := 0;
second <= '1';
elsif rising_edge(clk) then
if count < (max_count/2)-1 then
second <='1';
count := count + 1;
elsif count < max_count-1 then
second <='0';
count := count + 1;
else
count := 0;
second <='1';
end if;
end if;
end process;
end Timer;

 

[barry]

Looks a little more complicated than you need.

What I'd do (which doesn't necessarily make it right) is set max_count to 26999999, preload the counter to max_count and count down to zero. Every time counter=0, toggle second and reload the counter.