frequency divider using counter

viyaaloth · Apr 18, 2017

Hi ALL,

I need a clarification regarding frequency divider using counter.

Usually, If a counter with N bits, it will divide the frequency by 2^N.

Code Verilog - [expand]
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reg [19:0] counter;
 
   always@(posedge clk)  // clock frequency is 100MHZ
    begin 
        if(!reset_n)
            counter <= 0;
        else
        begin
            counter <= counter + 1'b1;
            clock   <= counter[16];
        end
    end

From the above snippet, what will be the frequency of "clock"

dipin · Apr 18, 2017

viyaaloth said:
Hi ALL,

I need a clarification regarding frequency divider using counter.

Usually, If a counter with N bits, it will divide the frequency by 2^N.

reg [19:0] counter;

always@(posedge clk) // clock frequency is 100MHZ
begin
if(!reset_n)
counter <= 0;
else
begin
counter <= counter + 1'b1;
clock <= counter[16];
end
end

From the above snippet, what will be the frequency of "clock"

hi

approximately 763 Hz (accurately :: 762.93)

regards

frequency divider using counter

viyaaloth

Junior Member level 3

dipin

Full Member level 4

viyaaloth

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Code Verilog - [expand]
1 2 3 4 5 6 7 8 9 10 11 12	reg [19:0] counter; always@(posedge clk) // clock frequency is 100MHZ begin if(!reset_n) counter <= 0; else begin counter <= counter + 1'b1; clock <= counter[16]; end end

frequency divider using counter

viyaaloth

Junior Member level 3

dipin

Full Member level 4

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