Thanks! Can you please elaborate a little?
In the attached picture, the yellow signal is the reset signal and they are the same for both simulations. According to your feedback, I think the green output signal looks correct because the output tracks the first rising edge of input after the reset clock becomes low. However, in the red simulation, the output tries to track the rising edge of the input while reset is still high...
Do you have any idea what could possibly cause that?
Thanks
Allen