this is the code for frequency divider but i am not getting the output wave for divided clock.....
also is there any rule or formula for dividing the frequency from 50mhz to some other value? like how many bits of counter to use ???
Code:
module clockdivider(clkdivout,reset,clk);
input reset,clk;
output clkdivout;
reg clkdivout;
wire reset,clk;
parameter period=10;
parameter halfperiod=period/2;
reg [3:0]countvalue;
always @(posedge clk)
begin
if(reset)
begin
countvalue = 0;
clkdivout <= 0;
end
else
begin
if(countvalue == period-1)
begin
countvalue = 0;
clkdivout <= 0;
end
else
countvalue = countvalue+1;
if(countvalue == halfperiod)
clkdivout <= 1;
end
end
endmodule
this is the code for frequency divider but i am not getting the output wave for divided clock.....
also is there any rule or formula for dividing the frequency from 50mhz to some other value? like how many bits of counter to use ???
if(reset)
begin
countvalue = 0;
clkdivout <= 0;
end
else
begin
if(countvalue == period-1)
begin
countvalue = 0;
clkdivout <= 0;
end
else
countvalue = countvalue+1;
if(countvalue == halfperiod)
clkdivout <= 1;
end
end
endmodule
PLZ can u tell how to force a clock signal to clk in simulation in modelsim 5.7... there is no option of force here....how will i check the simulation results?
---------- Post added at 13:04 ---------- Previous post was at 12:57 ----------
@deni i have changed the lines and given clock signal from forever command but i am not getting the ouput, both the clkdivout and countervalue are going x
No problems with your design. Why do you think it's not working? How did you test it?
Using a divided ("ripple") clock may be inappropriate in a synchronous design. But that's a different topic, I think.
P.S.: I don't see a problem of forcing a clock signal. You need to write a testbench that supplies the clock signal. Study respective Modelsim tutorials.
u can find the result in the image file below.
It proves that your code is right
So what you have to do next is to learn how to write a testbench for your every verilog project.