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frecuency stability in PLL

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Junior Member level 3
Jul 31, 2002
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Hello, my name is David.I`d like to know if the frecuency stability of the output signal in a PLL is the same as in the clock reference used in the loop.I mean, if the reference clock is 4 PPM, and the PLL has a multiplication factor x15 to obtain a 300 MHZ output signal, has this output signal also a frecuency stablity of 4PPM?does the PLL only make the phase noise of the output signal get worse?
I`ll be deligthed to know any link to application notes or articles related with this toipic.
Thanks in advance

generally the error in ppm at output is the same of signal in input.
You mast to take care to design the pll circuitry.

PLL stability

since PLL is supposed to lock with the reference clock. Output clock's stability will be "ALMOST" same.

i can upload a ref on PLL.


Measured over a longer time interval, the output frequency stability of the PLL is the same as of the reference signal.

If using a PLL you will also have to use a low-pass filter. Making the cut-off frequency of the filter higher will result in less phase-noise, but it will also lead to a larger amount of spurs from the reference frequency in the output signal of the PLL. Lowering the filter's cut-off frequency will make the PLL to be slower in adapting to changes of the reference frequency or division ratio (for example, if you want to have a PLL that can change it´s output frequency to various multiples of the reference frequency, then when changing that multiple the output frequency will take longer to stabilize).

To design a PLL is thus a question of compromising. You can not have a PLL that is excellent in every aspect so you will have to sacrifice performance in one area to gain performance in some other area.

Motorola once made a chip named MC4044. It was a PLL-chip and the associated data-sheets held a lot of useful information regarding the design of a PLL in principle, including the low-pass filter.


PLL Book

Here it is.. this is from NSC...


If the PLL sinthesyzer is single loop type then the PPM stability will not change. If it consists more loops, then you should calculate it by simple mathematics.

for PLL, the frequency stability is same as reference signal for all signals in PLL

thanks to all, I'll have a look to the ref smanish uploaded.
NOw, I have another problem.I'm also working with D.D.S. and I have to calculate the frecuency stability of the output signal generated in relation with the frecuency stability of the clock reference.I'm using a 2.5 PPM clock reference which becomes a 300 MHz clock inside the D.D.S. through its internal PLL with a x15 multiplication factor, then the D.D.S. generates a 120 MHz output signal:
is the frecuency stability of this 120 MHz output signal the same as the frecuency stability of the 20 MHz clock reference?
Do you know any specific link or application note related with this topic?
Thanks in advance again.

The reference accuracy will be retained even after a DDS circuit.
The effect of a DDS on the phase noise depends on the specific DDS, and you might need longer meausrement time to measure the original accuracy.

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