Yes.My question is...should I expect the noise shaping around output of divider ?
Strictly speaking, Noise shaping affects phase not voltage of output signal.How does the sigma delta controling cause the noise around the divider output to be shaped ?
I know why I see it at the modulator outptut
but I am not sure why should I see it at the divider output also.
Surely read my append in https://www.edaboard.com/showthread...equency-divider-using-Sigma-Delta-Modulator#2.Can you point the place where you see the noise shaping at my printscreen of freq divider output?
No.I understand the noise may be shaped not so efficient like at the modulator output
Surely consider bandwidth of spectrum.1:Why do not I see similar thing?
2:Why can't I see single product at the output frequncy? - there are many product near the output that have comparable magnitude.
delta_f=0.1kHz.I did another simulation for 10 ms,
Divide ratio is too small.fin 100 Mhz, div by 3 or 4.
Has anybody know why cant I see the peak at frequency (100MHz/3.5 (3.5 is div factor) )
I can not understand what you want to mean at all.and the noise shaping?
Surey learn very basic things.One more question: Does my Noise Shaping bandwidth (thats 50KHz) need to be in some relation with the output frequency of divider?
Can you surely understand very basics of DSM(Delta Sigma Modulator) ?I know why the noise shaping occurs in sigma delta
and can see it in the simulation of 2 nd order sigma delta (verilog model).
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For instance I have 10Meg divider input,
I am dividing it by 7 or 8 depending on sigma delta output - 0 or 1
No.YES, I am familiar with those two concepts
By definition."For small divide ratio such as 3.5, DSM PLL can not work." - will not work at all, by definiton?
Completely wrong.It is only verilog model based sigma delta and Dual Modulus Divider
- i should see somehow the noise shapping at the output
but I suppose my sigma delta samppling frequency is in wrong relation to input of frequency divider or something...
I don't think your sampling clock is 20kHz.So far I have used 10 MHz and 100 MHz as divider clock input
and mostly 20 KHz of SD samppling clock.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 analog begin @ ( initial_step ) begin vout_val = 1.0; hi=1.0; lo=-1.0; end @ (cross(V(vclk), 0))begin // summing junction vsum = V(vin) - vd ; // integrator vint = vsum + vint; // summing junction vsum2 = vint - vd ; // integrator vint2 = vsum2 + vint2; // quantizer if (vint2 > vth) vout_val = hi ; else vout_val = lo ; // D2A vd = vout_high * vout_val ; end V(vout) <+ transition(vout_val, tdel, trise, tfall); end endmodule
Simply you can not understand even very basic things at all.It seems I need to read more about SD modulators.
Completely wrong.I am using following verilog-A code for 2nd order SD modulator.
Possible for fisrt order DSM.Is there a chance I will see the noise shaping using 1 bit modulator to control DMD?
Surely see results.I am designing the secon order SDM using swich capacitor signal integrators, comparators, 1 bit DAC.
I see the noise shaping using my transistor based SDM circuit.
Simply lack of your ability.Why can't I see it using verilog-A model?
What you can not understand is not only DSM.I am starting working on SDM and do not understand some concepts
No.Does your explanation correspond to MASH type of Sigma Delta ?
Correct.If I understand you I can use only 1st order sigma delta for Dual Modulus Divider...
Correct.For higher orders I need to use MULTI modulus divider that has multi bits control signal...
You can not control frequency divider as target fractional divide-ratio.But what when my Second order sigma delta has one bit output like in this case?
Simply you can not understand anything.Is it also unusable to see noise shaping ?
Yes.but there is a lot of examples of 2nd order sigma delta that has 1 bit output.
SO What are they use for?
Are they used only for ADC/DAC conversion ?
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