TuAtAu
Advanced Member level 4
I descripe my BRAM in a .vhd and synthesized and it is workable.
But when I use them in lower hierarchy, It cannot instantiate as the BRAM!!
WHY?!? what's going wrong?
Bottom 2 pictures will explain everything.
My BRAM code:
1. BRAM SUCCESS in MEMORY UNIT
**broken link removed**
2. WHY NO BRAM?? BUT OVERFLOW my slice and gates!
**broken link removed**
But when I use them in lower hierarchy, It cannot instantiate as the BRAM!!
WHY?!? what's going wrong?
Bottom 2 pictures will explain everything.
My BRAM code:
Code:
architecture Behavioral of BRAM_2s14_49bit is
type BYTE_RAM_TYPE is array (0 to 16383) of std_logic_vector(48 downto 0) ;
signal BRAM : BYTE_RAM_TYPE:= (others => (others=> '0'));
begin
process (CLK)
begin
if (CLK'event and CLK = '1') then
if (ENABLE = '1') then
if (WRENABLE = '1') then
BRAM(conv_integer(ADDRESS(13 downto 0))) <= DATA_IN;
end if;
DATA_OUT <= BRAM(conv_integer(ADDRESS(13 downto 0))); --if correct, cache out
end if;
end if;
end process;
end Behavioral;1. BRAM SUCCESS in MEMORY UNIT
**broken link removed**
2. WHY NO BRAM?? BUT OVERFLOW my slice and gates!
**broken link removed**