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[SOLVED] [FPGA]Wierd instantiate in Xilinx FPGA

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TuAtAu

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I descripe my BRAM in a .vhd and synthesized and it is workable.
But when I use them in lower hierarchy, It cannot instantiate as the BRAM!!
WHY?!? what's going wrong?

Bottom 2 pictures will explain everything.
My BRAM code:
Code:
architecture Behavioral of BRAM_2s14_49bit is
	type BYTE_RAM_TYPE is array (0 to 16383) of std_logic_vector(48 downto 0) ;
	signal BRAM 				: BYTE_RAM_TYPE:= (others => (others=> '0'));
begin


	process (CLK)
	begin
		
		if (CLK'event and CLK = '1') then
			if (ENABLE = '1') then
				if (WRENABLE = '1') then
					BRAM(conv_integer(ADDRESS(13 downto 0))) <= DATA_IN;
				end if;
				DATA_OUT <= BRAM(conv_integer(ADDRESS(13 downto 0))); --if correct, cache out
			end if;
		end if;
	end process;
	
	
end Behavioral;

1. BRAM SUCCESS in MEMORY UNIT
**broken link removed**


2. WHY NO BRAM?? BUT OVERFLOW my slice and gates!
**broken link removed**
 

TrickyDicky

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I can only think of 2 things:
1. The connections arnt quite right in the 2nd picture
2. Its a synthesis bug.

For 1. Make sure clock, write enable and enable are all synchronous
2. Report the problem to Xilinx.
 
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    TuAtAu

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TuAtAu

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What do u mean by synchronous and asynchronous? Any example? Thanks.
 

TuAtAu

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add

attribute ram_extract : string;
attribute ram_extract BRAM is signal : "yes";

solved
 

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