Re: FPGA Verification!
The 'outside' world for VHDL code is the 'entity' declaration in the top part of your (top level) design. You define here the input and outputs.
At that point the input/outputs are defined, but it is yet unknown on what, physical, pins they are located on the FPGA. This is defined by a constraints file. This file typically has the .ucf extension. This file contains pinnames and there physical location. It typically also contains not only the name of the clock pin (which should also be part of your 'entity'), but also the 'timing' of that clock pin (how long on, off, ...).
When using the Xilinx ISE you can have the ISE 'generate' this constraints file for you (Pace/Floorplanner).