fpga to PC using SPI interface

[aroy]

Hi! I'm working on a data logging project which involves an ADC, FGPA and an SPI interface. The way I am going about it is the following:

1. parallel 14-bit data from the ADC is stored in registers inside the FPGA
2. when i send a command to start reading the data from the registers using the spi interface, the data in the registers is loaded into a parallel-in/serial-out shift register
3. the data from the shift registers is transferred across the MISO bus

the protocol of the spi is the following: 2 bytes of instruction (8-bit address followed by 8-bits of data) sent on the MOSI bus. once the fpga receives this instruction, the PISO accesses the correct register given by the address and starts the serial conversion.

I am a little confused about how to go about the difference in clock speeds. the fpga and the internal logic (PISO shift register) run @ 48 Mhz while the bitrate of SPI bus is 250 KHz. so if the PISO is converting parallel data into serial MUCH faster than the transfer rate, won't I start losing samples.

Or should the PISO convert data only at the rising/falling edge of the SPI clock. i was also looking into whether i need to synchronize the two clocks using 2 D-FFs.

any insight into this is appreciated. thanks!

 

[shaiko]

A few questions:

1. What is the SPI interfaced to ?
2 .What is the conversion rate of your ADC ?

You can use a FIFO to store samples - but if the ADC sends information all the time and at a higher rate than your SPI can "get rid" of it - the FIFO will evantually overflow.

Knowing the convertion rate of your ADC is key - the fact that your FPGA runs at 48MHz doesn't mean that the ADC also runs at that speed.
Regarding the MISO input to the FPGA - yes it should be sampled with 2 D-FF.

 

[aroy]

A few questions:

1. What is the SPI interfaced to ?
2 .What is the conversion rate of your ADC ?

You can use a FIFO to store samples - but if the ADC sends information all the time and at a higher rate than your SPI can "get rid" of it - the FIFO will evantually overflow.

Knowing the convertion rate of your ADC is key - the fact that your FPGA runs at 48MHz doesn't mean that the ADC also runs at that speed.
Regarding the MISO input to the FPGA - yes it should be sampled with 2 D-FF.

1. I am using an Aardvark adapter which has SPI on one end and USB on the other to log the data to a PC.
2. The way the board has been developed, both the ADC and the fpga share the same clock..so 48 MHz.

What I can maybe do is downsample the incoming waveform inside the FPGA so that the FIFO doesn't overflow as quickly. But the problem of parallel to serial conversion happening faster than the transfer still remains.

 

[shaiko]

Please provide the ADC's datasheet.

 

[aroy]

1. I am using an Aardvark adapter which has SPI on one end and USB on the other to log the data to a PC.
2. The way the board has been developed, both the ADC and the fpga share the same clock..so 48 MHz.

What I can maybe do is downsample the incoming waveform inside the FPGA so that the FIFO doesn't overflow as quickly. But the problem of parallel to serial conversion happening faster than the transfer still remains.

I should also clarify that the FPGA in this case is the slave.

 

[shaiko]

OK
It will help to see the datasheet of your ADC

 

[aroy]

Please provide the ADC's datasheet.

https://www.analog.com/static/imported-files/data_sheets/AD9649.pdf

 

[shaiko]

Read this note on page 7 of the datasheet:
"Conversion rate is the clock rate after the CLK divider"
You can read more about the divider on page 20