TenmaNeko
Newbie level 6
Hello all, I wasn't sure where else to post this; I apologize if it's the incorrect forum.
We are using an FPGA to interface with an Intel 80386DX processor. All processor signals pass though the FPGA. Within the FPGA we are emulating the DMA controller (82380) using a COTS IP core we purchased. Our system will run fine, but occasionally when we change something seemingly unrelated to direct processor control, it will cause the processor to freeze.
This is what occurs:
1. Hold processor in reset
2. Program FPGA
3. Release reset
4. Processor functions correctly
5. Reset processor again
6. Processor reads first address, gets correct data (reset vector) and then freezes
We send it the next READY signal properly, but no new address and no ADS is produced by the processor.
HOLD is not being activated, and reset isn't being asserted again.
The problem persists over any number of resets until power is cycled and the FPGA reprogrammed.
It seems to be related to the FPGA timing, somehow. As an example, we ran the one of our clock signals out to a test point, and that "cured" the problem. However, that is obviously not a good permanent fix. The clock we send out to the processor is stable and consistent.
So, does anyone have any experience with this processor that could shed some light on what would cause it to lock up? Or does anyone know of some 386 resources that may contain a solution?
Thanks all!
We are using an FPGA to interface with an Intel 80386DX processor. All processor signals pass though the FPGA. Within the FPGA we are emulating the DMA controller (82380) using a COTS IP core we purchased. Our system will run fine, but occasionally when we change something seemingly unrelated to direct processor control, it will cause the processor to freeze.
This is what occurs:
1. Hold processor in reset
2. Program FPGA
3. Release reset
4. Processor functions correctly
5. Reset processor again
6. Processor reads first address, gets correct data (reset vector) and then freezes
We send it the next READY signal properly, but no new address and no ADS is produced by the processor.
HOLD is not being activated, and reset isn't being asserted again.
The problem persists over any number of resets until power is cycled and the FPGA reprogrammed.
It seems to be related to the FPGA timing, somehow. As an example, we ran the one of our clock signals out to a test point, and that "cured" the problem. However, that is obviously not a good permanent fix. The clock we send out to the processor is stable and consistent.
So, does anyone have any experience with this processor that could shed some light on what would cause it to lock up? Or does anyone know of some 386 resources that may contain a solution?
Thanks all!