FPGA-to-HPS SDRAM Bridge in Bare-metal

Mechatronics_eng · Sep 26, 2016

I am using DE1-SoC to start bare-metal programming for dual-core Cortex-A9 ARM hard processor, Cyclone V.

I'm trying to read data from SDRAM to FPGA using FPGA-to-HPS SDRAM Bridge.

I configured FPGA-to-HPS SDRAM interface in qsys to use avalon-MM Read only, 32 width.
I exported FPGA-to-HPS SDRAM Bridge avalon-MM Read only and write verilog state machine for reading
..

Code Verilog - [expand]
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always @ (posedge DDR3_clk )   
begin
 if(sdramState == READ) begin
  DDR3_read <=1'b1;
  DDR3_write <=1'b0;
  if(DDR3_waitrequest==1'b0 && DDR3_read==1'b1)begin
   if(!wrfull_vga_fifo ) begin
    if(sdram_rd_cnt == (0 + 110591) ) begin
     sdram_rd_cnt <= 0;
    end else begin
     sdram_rd_cnt <= sdram_rd_cnt + 1'b1;
    end   
    DDR3_address <= sdram_rd_cnt; //+ A_FRAME_SA;
    data_to_vga <= DDR3_readdata[15:0];
    wrreq_vga_fifo <= 1'b1;   
   end else begin
    wrreq_vga_fifo <= 1'b0;
   end
 
  end else begin
   wrreq_vga_fifo <= 1'b0; 
  end
 end
end

And I build preloader using bsp-editor.exe and load it using Eclipes of DS-5.

When I traced FPGA-to-HPS SDRAM Bridge "avalon-MM Read only signals" on signalTab, The output was:
avalon_DDR3_waitrequest signal was always 1.

Then I added in main():

Code:

alt_bridge_init(  ALT_BRIDGE_F2S, NULL, NULL);

The output was:
avalon_DDR3_waitrequest became 0 but still no data read ( avalon_DDR3_readdatavalid was always 0, and avalon_DDR3_readdata was always 0).

FPGA-to-HPS SDRAM Bridge in Bare-metal

Mechatronics_eng

Newbie level 4

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FPGA-to-HPS SDRAM Bridge in Bare-metal

Mechatronics_eng

Newbie level 4

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