FPGA synthesizable verilog code with floating point numbers

[akipro]

I'm trying to implement a linear programming problem on FPGA. I have used real data type to generate floating point numbers. The program compiled fine, but when I'm trying to synthesize it for my Xilinx Spartan-3E FPGA board it shows error that real is not supported by verilog. It seems that we cannot use real for synthesizable codes. So any suggestions on how to remove this error.

 

[axcdd]

real type is not synthesizable.
Generally use real library for generating constants in code only. You have to convert floating point numbers to fixed point.

 

[FvM]

Real is not floating point. Floating point is synthesizable by using respective libraries (IP blocks, coregenerator, Megafunctions whatsover). But it's very resource consuming and fixed point is the better solution in many cases.