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FPGA resource utilization and power consumption

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Sumathigokul

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Is there any relationship among resource utilization and total power consumption of digital design??? If it is so, then can you justify the the following ??? (generated using Libero IDE)
Design 1:
Core Cells: 7 of 260 (3%)
IO Cells : 10
Total power consumption : 4.998 mW
Static power consumption : 1.56 mW
Dynamic power consumption : 3.438 mW

Design 2:
Core Cells: 20 of 260 (8%)
IO Cells : 11
Total power consumption : 4.369 mW
Static power consumption : 1.23 mW
Dynamic power consumption : 3.139 mW

How is it possible that higher circuit utilization reduces its total power consumption????
 

TrickyDicky

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Power consumed is higher only when a register changes state. So if you have a large design that doesnt do a lot at a low clock frequency it will probably use a lot less power than a very small design running at a high clock frequency with a high % of change.
 
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Sumathigokul

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Switching frequency is related to dynamic power whereas leakage power is static power. My doubt is design with more no. of transistors i.e. gates should consume more static power than one with less no. of gates right???
 

verylsi

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Hi Sumathigokul,

Nice question. Please post the answer if you find it from other sources too.
BTW, can you please elaborate, which device you are using and what is your operating speed ?
 

Sumathigokul

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Hi Sumathigokul,

Nice question. Please post the answer if you find it from other sources too.
BTW, can you please elaborate, which device you are using and what is your operating speed ?

I have synthesized the design using ProAsic3, A3PN010 with 100 MHz frequency.
 

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The two testcase designs, can you post them? That might give some insight as to why they have the power numbers they do.

Suppose, if one design is a ring oscillator and the other design is a mux. I would expect the ring oscillator with less gates to consume more power than the mux. So it may be you are performing apples to oranges circuit comparisons.

Also if you want "accurate" numbers you usually have to perform netlist simulations on the design (I don't believe you need to annotate with SDF) and output VCD files for multiple typical simulation runs to produce enough data to get an accurate estimation of the toggle rates of all nodes in the design, which are then used in the power calculation spreadsheet provided by the vendor. e.g. Xilinx power estimator has an error of something like +/-30% with just estimating by utilization. This goes down to <+/-5% (don't remember the real numbers, and I'm not willing to waste time looking it up, as it's quoted right on the power estimator spreadsheet notes) with good vectors to determine accurate toggle rates.
 
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