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FPGA power supply

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engr_joni_ee

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Hi, I just found this schematic from a FPGA development board. They have used MAX 15301 for VCCINT but is this really 40 A power supply ? I have looked at the datasheet which says "High Output 2A/4A MOSFET Driver" but I don't find anything like 40 A. Kindly have a look and reply if you can explain this. Thanks in advance.


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Hi,

The main question should be: How much current do you need?
Do you need 40A?

Klaus
 

2A/4A is MOSFET gate current. The synchronous buck converter is obviously designed for 40 A output current. By the way, if you scroll down on the linked product page, it says 25 A capability, that's at least the order of magnitude.

Do you need 40A core supply in your FPGA application? Most likely not, but a development board is designed to support applications with maximal core switching activity.
 

High gate current also means high drain to source current in MOSFET in general ? Regarding MAX 15301, is this linear regulator or a buck converter or any other type power supply.

I don't think that my application need such a high current on VCCINT but which manufacturer I can find similar devices and is there any recommendation on selecting such devices.
 

Regarding MAX 15301, is this linear regulator or a buck converter or any other type power supply.
The say "switched mode power supply controller", what do you guess?

FPGA vendors have application guides for power supply solutions, also all major manufacturers of power managment ICs.
--- Updated ---

High gate current also means high drain to source current in MOSFET in general ?
There's a relation, but not that simple. Static gate current of switcher MOSFET is very small, but dynamic currents can be high, depending on gate capacitance and intended switching speed. Gate capacitance is related to transistor area respectively rated current. Switching speed is generally high with high efficiency SMPS. So you finally get a relation between SMPS output current and gate driver current requirement.
 
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High gate current also means high drain to source current in MOSFET in general ? Regarding MAX 15301, is this linear regulator or a buck converter or any other type power supply.

I don't think that my application need such a high current on VCCINT but which manufacturer I can find similar devices and is there any recommendation on selecting such devices.
No. High gate current means fast switching speed. It has absolutely nothing to do with drain current.
 

I also notice that there are four power FETs but I am not getting how they are connected with other components to supply that much current. Do we have other option to get 1 V @ 40 A using DC to DC converter from 12 V ?
 

there are plenty of other solutions on the net for buck converters to supply 1v0 @ 40A, happy searching ....

but the given Xylinx circuit seems not a bad option, 400kHz may prove interesting tho
 

there are plenty of other solutions on the net for buck converters to supply 1v0 @ 40A, happy searching ....

but the given Xylinx circuit seems not a bad option, 400kHz may prove interesting tho
Do you mean it's a nice design because it works with lower switching frequency 400 KHz ? Can you please explain the circuit ?
 

You should probably buy the dev board and read all the documentation thoroughly - this is not a project for some one with no power electronics experience
 

Hi,

There are ready to buy POL (point if load) power supply modules.Look at distributors.
I have some spare 1.8V/40A modules ... in case you are interested in...

Indeed I guess it's no good idea to design them on your own. (As long as you are not experienced in designing SMPS)

Klaus
 

What is POL (point of load) in the MAX 15301 ?

In which document I can find power supply guideline for ultrascale kintex ? I am not designing the power supplies my own but trying to understand how the power circuit works for KCU 105
 

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Hi,

POL just means you have a common (high voltage) power supply ... and near the load (point of load) you have a DCDC buck converter.

Klaus
 

Big FPGAs can pull over 10A on the low voltage main core rail.
This is of course very config and application dependent. They
also assert in some cases, pretty fussy sequencing / ratiometric
behavior at power-up and power-down.

A "shrink fit to specific FPGA" power solution would (one hopes)
have taken care of these "secondary" issues and provide some
close-in layout style and BOM guidance, all of which will be
handy. At 0.9V core you will have about 50mV of "recommended"
tolerance on the rail and 200mV from nominal you'll see damage
(high) or retention loss (low) on SRAM cells - at least, according
to datasheets. There's doubtless some padding. You don't get
to know how much. So, 50mV/10A=5mOhm from POL filter / FB
(and ground, coming back) total layout resistance. And that's
if you're of a mind to allow near-low-limit supply sag.

Study the eval board layouts you can find Gerbers for, to get
ideas about routing priorities, styles, placement, weights & widths,
etc.
 

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