FPGA pin assignment,How to do good pin assignment for design

Hi Guys,
I am not clear about pin assignment to i/o in your design in xilinx environment.

First of all does it really give you a big speed advantage if you assign pins to i/o in your design?

If so, how to make a good pin assignment to i/o in your design? e.g,) i am working on AES (advanced encryption standar) in xilinx ise. I want to know whats the maximum speed of my implementation? Does making a good pin assignment to i/o in the design help in achieving best possible speed?

Any one who has synthesized AES or similar design, please share your thoughts.

Re: FPGA pin assignment,How to do good pin assignment for de

Hi,

Many FPGAs have flip-flops built into the input and output buffers to optimize
the timing in and out of the chip. Along with these special I/O buffers will be an
optimization to enable or disable the packing of these registers into the I/O.
Figure 16.8 illustrates the concept of packing registers into the I/O buffers.



There are a number of advantages to placing a register in the I/O:
. The delays at the I/O of the FPGA are minimized.
. More logic is available internally.
. Superior clock-to-out timing.
. Superior setup timing.

The disadvantage of this optimization is that a register that is placed in an
I/O buffer may not be optimally placed for the internal logic as shown in
Figure 16.9.



For high-speed designs that have tight timing requirements at both the I/O
and the internal logic, it may be advantageous to add another layer of pipeline
registers at the I/O if allowed by the design protocol as shown in Figure 16.10.



If there are a large number of I/O registers, the extra pipeline layer may add
significant overhead in terms of register utilization and potentially congestion.

An extra pipeline register may be required for high-speed designs when packing
registers into I/O.

Thus, if there are not tight I/O timing requirements and there are a relatively
large number of I/O registers, this optimization is not recommended.

HTH
--
Shitansh Vaghela