FPGA LVDS-receiver input capacitance

[MC-Electric]

Hello,

I am currently designing a LVDS standard interface to drive a Virtex-6 FPGA with 1.25Gbps (DDR) and I would like to know if the corresponding values for the input capacitance of the LVDS-pins in the data-sheet or IBIS-file are valid? With a normal LVDS interface (I=3.5 mA and Rd=100 Ohm) it is to my mind not possible to drive 6-8pF single-ended input capacitance at 1.25Gbps. What do I misunderstand, because the data-sheet says that it is possible to drive the Virtex-6 at 1.25Gbps with a standard LVDS driver? Are the values right?

I´m grateful for any help regarding this topic.....

Cheers,
MC-Electric

 

[farhada]

Hi,
I think this is a question you should send to Xilinx discussion groups rather than here.

Best regards,
Farhad

 

[ibrahim.ahmed]

hi MC-electric
Have you found an answer to your question? Because I need to know the input capacitance of an LVDS reciever on a virtex6 FPGA ???

Thanks in advance
Ibrahim AHmed