FPGA INIT pin function

[hithesh123]

I don't understand the function of INIT pin completely.
When the progB pin goes low, the Init pin goes low indicating the FPGA is clearing it's registers.
But the ug332, also says by holding INIT Low the configuration can be delayed.
If the FPGA is driving INIT. How can the user(external logic like MCU) hold it low to delay the config.?

 

[FvM]

The INIT_B details are explained e.g. in Xilinx Configuration User Guide. It's an open drain pin.