FPGA design synthesis issue

[dll_fpga]

hello ,
i have generated a blockram using coregen and it has a we[0:0](write enable)
i dont need that so ,i need to keep this always enabled.....
so how can this be done?
in the toplevel module calling this block with 1'b1 is ok...?


ie

bram u1(.we(1'b1),.dina(dina......)

is that ok?
will this code connect we[0:0] to vcc?

 

[kirill]

hi
It is ok, if you will assign new data to databus every clock cycle.

 

[permute]

I'm not certain its the best idea. From what I recall, there can be issues if you also want to initialize the BRAM. IIRC, issuing writes during reset can corrupt multiple locations of RAM. If you don't use any initial values, then you're probably ok. From a simulation perspective, you will get a handful of warnings -- write collisions and writes within 3 cycles of reset.