The only real limit is the speed grade of the FPGA. I have done this in excess of 250 MHZ. If the register based clock feeds a lot of flops, then you need to use a global clock buffer to reduce the clock slew between the flops receiving the clock. Generally, I would instantiate the clock buffer explicitly in the HDL code.
If your register generated clock only feeds a few flops, then local clock routing is usually sufficient. If you spec your clock periods accurately in the constraints file, then FPGA place and route tools should configure the routes and placement to insure that your design works.