chrgol
Newbie level 1
Hi Everyone,
I'm fairly new to FPGA programming and this is my first post on the forum. I'm currently building a new camera using an Artix-7 FPGA and the Vivado design suite (using verilog). The image sensor supplies its data via 8 LVDS DDR lines and 1 LVDS clock. So far, the project is going well. I've managed to get an image off the sensor and view it properly on my PC. However, there are a few changes I need to make in order to finish the design and unfortunately I'm running into some problems. The main one is that everytime I make change (however small) the timing of the data becomes invalid. In order to solve the timing issue in the first place, I used an IDELAYE2 on each channel coming in and then adjusted the IDELAY_VALUE until it worked (Not the best way, I know, but it got it working). I have also read through this document:
https://www.xilinx.com/support/documentation/application_notes/xapp855.pdf
Which suggests you can calculate the timing delay dynamically (which would be our preferred options), but doesn't seem to give you any code to show you how to do it. I've searched around but am unable to find a good resource for this.
Another suggestion I have been given is to add constraints into the design (which will help fix the design and avoid the timing issues). When we've tried this, the build time goes from 2-3 mins to 20+ mins making it very inconvenient. Perhaps this is a sign we are doing something wrong? The build time issue occurs even if I add just the following line:
create_clock -period 3.367 -name lvdsClkP [get_ports lvdsClkP]
So I Guess what I asking is the following:
1) What's the best way to dynamically adjust the IDELAYE2?
2) How can I constrain my design without increasing the build time?
3) Are there any good resources I can be pointed to in order to help with these issues.
Any help would be greatly appreciated. I'm happy to give more details if (when) necessary.
Chris.
I'm fairly new to FPGA programming and this is my first post on the forum. I'm currently building a new camera using an Artix-7 FPGA and the Vivado design suite (using verilog). The image sensor supplies its data via 8 LVDS DDR lines and 1 LVDS clock. So far, the project is going well. I've managed to get an image off the sensor and view it properly on my PC. However, there are a few changes I need to make in order to finish the design and unfortunately I'm running into some problems. The main one is that everytime I make change (however small) the timing of the data becomes invalid. In order to solve the timing issue in the first place, I used an IDELAYE2 on each channel coming in and then adjusted the IDELAY_VALUE until it worked (Not the best way, I know, but it got it working). I have also read through this document:
https://www.xilinx.com/support/documentation/application_notes/xapp855.pdf
Which suggests you can calculate the timing delay dynamically (which would be our preferred options), but doesn't seem to give you any code to show you how to do it. I've searched around but am unable to find a good resource for this.
Another suggestion I have been given is to add constraints into the design (which will help fix the design and avoid the timing issues). When we've tried this, the build time goes from 2-3 mins to 20+ mins making it very inconvenient. Perhaps this is a sign we are doing something wrong? The build time issue occurs even if I add just the following line:
create_clock -period 3.367 -name lvdsClkP [get_ports lvdsClkP]
So I Guess what I asking is the following:
1) What's the best way to dynamically adjust the IDELAYE2?
2) How can I constrain my design without increasing the build time?
3) Are there any good resources I can be pointed to in order to help with these issues.
Any help would be greatly appreciated. I'm happy to give more details if (when) necessary.
Chris.