Expecting a transistor size of 28x28 nm (it's quite bit bigger, 28 nm is the structure measure) would result in a 0.5*0.5 mm square chip, duplicate by 5 or 10 and get the correct request of extent…
When meaning ASIC, you'll look to the real LUT use measurement which reveal to you which part of the LEs is used. You'll additionally think about that a huge offer of the aggregate transistor check is utilised for arrangement purposes.
Another point to consider is that other than rationale components, additionally more mind boggling assets like multipliers and memory can be used. They are utilising FPGA transistors substantially more proficiently, sparing in the ASIC interpretation is separately lower.