four pwm phase offset output with variable pwm frequency

Status
Not open for further replies.

I don't understand the question. A pwm frequency is not input into the design, a duty (cycle) and the clk (system clock) are used to determine the PWM frequency.

Maybe you want to change the period of the pwm pulses?
Code VHDL - [expand]
1
2
3
4

GENERIC(
       sys_clk         : INTEGER := 50_000_000; --system clock frequency in Hz
      pwm_freq        : INTEGER := 100_000;    --PWM switching frequency in Hz
      bits_resolution : INTEGER := 8;          --bits of resolution setting the duty cycle


The first three generics change that, by modifying the relationship between sys_clk and pwm_freq and the resolution of the duty cycle.
 

It should work if you input the frequency as a period signal.
 

FvM said:
It should work if you input the frequency as a period signal.
Click to expand...

The code already computes the PWM period.
Code: 
CONSTANT  period     :  INTEGER := sys_clk/pwm_freq;   --number of clocks in one pwm period

So the OP doesn't have to modify any code to change it. They just need to set new values for the 3 generics to get the required resolution and period, based on their system clock.
 

So the OP doesn't have to modify any code to change it. They just need to set new values for the 3 generics to get the required resolution and period, based on their system clock.
Click to expand...
To make the period variable, it has to be changed from generic to signal, together with a respective width generic. Also a check for required minimal value may be suitable. But you don't need any structural changes of the design.
 

With writing signal period : INTEGER := some constant , I can using this vhdl code to output any pwm frequency , thanks all of your help !!
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…