four pwm phase offset output with variable pwm frequency

[lgeorge123]

I found a web site gives pwm generator with multiple phases output ,however it is supposed the pwm frequency is given , what should I modify the code so that any pwm frequency can input to the vhdl code ??


https://eewiki.net/pages/viewpage.action?pageId=20939345#PWMGenerator(VHDL)-PortDescriptions

 

[ads-ee]

I found a web site gives pwm generator with multiple phases output ,however it is supposed the pwm frequency is given , what should I modify the code so that any pwm frequency can input to the vhdl code ??

https://eewiki.net/pages/viewpage.action?pageId=20939345#PWMGenerator(VHDL)-PortDescriptions

I don't understand the question. A pwm frequency is not input into the design, a duty (cycle) and the clk (system clock) are used to determine the PWM frequency.

Maybe you want to change the period of the pwm pulses?

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Code VHDL - [expand]
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GENERIC(
       sys_clk         : INTEGER := 50_000_000; --system clock frequency in Hz
      pwm_freq        : INTEGER := 100_000;    --PWM switching frequency in Hz
      bits_resolution : INTEGER := 8;          --bits of resolution setting the duty cycle

---

The first three generics change that, by modifying the relationship between sys_clk and pwm_freq and the resolution of the duty cycle.

 

[FvM]

It should work if you input the frequency as a period signal.

 

[ads-ee]

It should work if you input the frequency as a period signal.

The code already computes the PWM period.

CONSTANT  period     :  INTEGER := sys_clk/pwm_freq;   --number of clocks in one pwm period

So the OP doesn't have to modify any code to change it. They just need to set new values for the 3 generics to get the required resolution and period, based on their system clock.

 

[FvM]

So the OP doesn't have to modify any code to change it. They just need to set new values for the 3 generics to get the required resolution and period, based on their system clock.

To make the period variable, it has to be changed from generic to signal, together with a respective width generic. Also a check for required minimal value may be suitable. But you don't need any structural changes of the design.

 

[lgeorge123]

With writing signal period : INTEGER := some constant , I can using this vhdl code to output any pwm frequency , thanks all of your help !!