In rtl code there are a 8 bit reg and the reg[5:3] have a constant value "0", in netlist these three bit were TIEL, but formality reports these three bit unmatched points in reference object, why? What should I do now? Thanks.
I think the error is becase the constant dff synthesis to a wire tie to constant. You should find some command such as " seq_constant" . I just use lec , and at lec my command is " set flatten model -seq_constant". you should find the command in the manual .
because start from DC0412, constant register will be delete. you can
set compile_delete_unloaded_sequential_cells false
or set_dont_touch on the constant_register,
Some design can't avoid these unmatched points. For example, low power design with power compiler enable. Some gated clocks are implemented in destination netlist which are unmatched point compared with reference(RTL)