Alvin80
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formality clock gating
Hi everybody,
I'm a newbie of Formality tool environment.
I applied my own clock-gating technique on a design and I would like to validate that the optimization doesn't corrupt the behaviour of the design.
Functional verification passed usign NCSIM.
Formal verification didn't pass usign Synopsys Formality.
It seems that the tool doesn't manage the comparison between design with and without clock-gating (I also tried Synopsys standard clock-gating ). I suppose that it is impossible. The differences are at the inputs of the FF, but the outputs are the same both in the reference design and in the implemented design.
I found the variable 'verification_clock_gate_hold_mode' and I set it using all the different values (any, low, high).
Where could the problem be?
Hi everybody,
I'm a newbie of Formality tool environment.
I applied my own clock-gating technique on a design and I would like to validate that the optimization doesn't corrupt the behaviour of the design.
Functional verification passed usign NCSIM.
Formal verification didn't pass usign Synopsys Formality.
It seems that the tool doesn't manage the comparison between design with and without clock-gating (I also tried Synopsys standard clock-gating ). I suppose that it is impossible. The differences are at the inputs of the FF, but the outputs are the same both in the reference design and in the implemented design.
I found the variable 'verification_clock_gate_hold_mode' and I set it using all the different values (any, low, high).
Where could the problem be?