Formality LEC --- FE-LINK-2

[ASIC_intl]

I have a memory instantiated as a black box in my gate level netlist . That black box is a memory for which a library (.db) exists. From that .db file the memory is picked up when synthesis runs.

While doing LEC by formality there is an error that arises because of port mismatch. But there is no port mismatch for that memory actually between the RTL and get level netlist. Is it that the memory should be set as black box in formality script to avoid this error? THIS ERROR CODE IN FORMALITY IS FE-LINK-2

 

[lostinxlation]

Does LEC work with .db nowadays ? When did Cadence make it work that way ?

Anyway, make the hard macros black boxes.

 

[ASIC_intl]

Lostin

I am not getting what you mean by -------- Does LEC work with .db nowadays ? When did Cadence make it work that way ?

I WORK WITH FORMALITY.

IS IT MANDATORY TO make the hard macros black boxes ?

Is it mandatory

 

[lostinxlation]

oh, ok, I missed that because, upper case, LEC reminded me of Verplex. Sorry about that.

While doing LEC by formality there is an error that arises because of port mismatch. But there is no port mismatch for that memory actually between the RTL and get level netlist.

if you are using .db file, you should check the pin matching between your RTL/netlist and .db(.lib) as well.
If the pin mismatching is between RTLs and netlists, I'd guess it won't cause ERROR. It rather reports as mismatches.

 

[ASIC_intl]

What you have written if what FE-LINK-2 says.


IS IT MANDATORY TO make the hard macros black boxes?

 

[lostinxlation]

.db would work. If not, it's because your netlist/RTL and the library have some inconsistency like pin mismatches.

 

[sp]

u need to black box both golden and revised for that ram so that the tool can do mapping and comparison, also i think this is not cadence lec but it's synopsys formality.