You can't tell why it fails just by looking at the end flop. THe problem is somewhere in the logic cone contributing to the failing flop or just simply mapping failure.
First, make sure no flops are left unmapped. Post the failure log.
Are you giving SVF file as guidance to Formality. This file generated from DC/DCT and DC generates it automatically. If you did not give this file to Formality, then first read this file and set the synopsys_auto_setup variable to true.
normaly the LEC tool didn't make mistake. But it could
a-you must never modify your RTL code to pass LEC, or you can follow some guideline provide by the LEC tool provider.
b-when it failled you need to analyze the log to check any missing files, library, missing mapping point...
c-you can also do LEC hierarchicaly to find which sub-module failled and reduce the design size to be able to find which rtl code is not correctly synthesis or not correctly LEC.
d-The problem can come from the syntheser or the Logic Equivalent Tool.