formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011

[billyc59]

formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011

Hi,

I'm trying to load my Synopsys design compiler-generated netlists into formality and I am getting the above error.

use of undeclared identifier "std_logic vector" FMR_VHDL-011

I'm very confused by this issue as the netlists were generated by a tool and not hand-coded. This particular module is also the top-level design file for my entire project. the sub-modules have no trouble being loaded. This error is occuring when I try to load the implementation files, and not the RTL reference files. Does Formality recognize module dependancy?

please help.

 

[kornukhin]

Re: formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011

Can you post your formality script here?

 

[billyc59]

Re: formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011

I'm not using a script per-se. I'm using the gui.

 

[kornukhin]

Re: formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011

I am not sure that DC can write netlist with wrong syntax.
So it must be formality setup error. Try to write TCL script, it helps to find solution.

By the way how many VHDL files do you read?
From FM UG:
"When you specify more than one VHDL file to be read with a SINGLE read_vhdl command, Formality automatically ATTEMPTS TO READ
your files in the CORRECT ORDER. If the list of files includes VHDL configurations, this feature does not work.
Disable it by setting the hdlin_vhdl_strict_libs variable to false before using the read_vhdl command.
If you are using MULTIPLE read_vhdl commands, you must issue them in the CORRECT COMPILATION ORDER."

 

[billyc59]

Re: formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011

vhdl files: at least 300.

Can formality recognize underscored numbers? Formality complained about not having the correct reference to a module that was named XXXX_2 to one named XXXX_2_0_0_0 (all generated by DC)

I have since edited this out and seemed to have reduced the number of error messages, but there is another issue.

DC seemed to have made a component instantiation using 2 lines of the same name. The port is also not an inout.

architecture SYN_rtl of HW_x_f_C_block2 is
--small hand modification to the netlist. instead of 3_0_0_0, just 3
component HW_x_f_C_block2_DW_mult_tc_3 --_0_0_0
port( product : in std_logic_vector (8 downto 0); b : in
std_logic_vector (26 downto 0); product : out std_logic_vector (35
downto 0));
end component;

Thank you for your help so far. I really appreciate the effort.

---------- Post added at 16:40 ---------- Previous post was at 15:27 ----------

after more modifications to the netlist, I managed to get it to read. The problem now comes in setting the top-level module. Formality says that no binding exists for a sub-module during the elaboration of the module's instance. What could typically cause this issue?

 

[kornukhin]

Re: formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011

I am using Verilog, but I think for VHDL there is no differences. Here is an example of simple (but working) formality script:

read_verilog -container r -libname WORK { ../../sources/rtl/filter.v ../../sources/rtl/top_ctrl.v }
set_top r:/WORK/top_ctrl -parameter { WIDTH=32, SYNC=2 }

read_verilog -libname WORK -netlist -container i ../net/top_ctrl_32_2.v
read_db -i { ../db/stdlib_013.db }
set_top i:/WORK/top_ctrl_WIDTH32_SYNC2
set_implementation_design i:/WORK/top_ctrl_WIDTH32_SYNC2
verify

 

[billyc59]

Re: formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011

I'm doing all of those steps, including setting hdlin_warn_on_mismatch_message tabs to treat the bulk of my errors into warnings. My problem now is a binding issue.

No binding exists for instance XXX1 during elaboration of instance top_level/XXX0/XXX1 FMR_VHDL-433
have you seen this error before? there is next to no documentation on this error.