Re: formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011
I am not sure that DC can write netlist with wrong syntax.
So it must be formality setup error. Try to write TCL script, it helps to find solution.
By the way how many VHDL files do you read?
From FM UG:
"When you specify more than one VHDL file to be read with a SINGLE read_vhdl command, Formality automatically ATTEMPTS TO READ
your files in the CORRECT ORDER. If the list of files includes VHDL configurations, this feature does not work.
Disable it by setting the hdlin_vhdl_strict_libs variable to false before using the read_vhdl command.
If you are using MULTIPLE read_vhdl commands, you must issue them in the CORRECT COMPILATION ORDER."