Formality between pre-layout and post-layout net list ????

[nawaz.mjcet]

hi all,
i have following questions to ask while doing formality between pre-layout and post-layout netlist:

1. do we apply any constraints ??

2. do we check LEC by enabling scan logic or or we disable scan logic.

please tell me the exact procedure to do LEC between prelayout and postlayout netlist...pls reply ASAP.

Thakns in Advance,
-Nawaz.

 

[rca]

you need to disable the scan mode.

this thread already explain this:

https://www.edaboard.com/threads/250967/

---------- Post added at 19:54 ---------- Previous post was at 19:54 ----------

https://www.edaboard.com/threads/250967/

 

[nawaz.mjcet]

yeah.....so you mean to say...using FORMALITY tool we only check only function logic between reference and implementation....not the test logic i.e scan logic???

 

[rca]

Only the test logic inserted by the tool like for scan could not be covered by LEC. nand-treee or other stuff that already inside the RTL code are covered.