Re: Formal Verification
FV does equivalence checking between two designs. If a design is functionally verified then any further modifications to that design is formally verified with original design. This avoids multiple functional verification.
FV is generally done after DFT, BIST insertion to avoid functional verification again. The DFT,BIST logic is disabled and the netlist without DFT, BIST is formally verified with DFT,BIST inserted netlist.
FV takes less time compared to functional verification and is extensively used in industries.