xuexucheng
Full Member level 2
Hi, nice guys,
As you konw, the GWE of XILINX FPGA is synchronous to config clock. If the GWE released at the user clock edge, could the D flipflop misfunction?
I find something which confused me. The D flipflop's init value is 0. The D flipflop is set to SRLOW. The D input is connected to logic 1, the SR is also connected to logic 1.
I think the SR is high prioprity. So the D flipflop should be 0 at output. But we can get a clock cycle of logic 1 occasionally at the D output when start up.
Could anybody give some comments?
Thanks in advance!
As you konw, the GWE of XILINX FPGA is synchronous to config clock. If the GWE released at the user clock edge, could the D flipflop misfunction?
I find something which confused me. The D flipflop's init value is 0. The D flipflop is set to SRLOW. The D input is connected to logic 1, the SR is also connected to logic 1.
I think the SR is high prioprity. So the D flipflop should be 0 at output. But we can get a clock cycle of logic 1 occasionally at the D output when start up.
Could anybody give some comments?
Thanks in advance!