For the design a 10 bit far adc, what should be the maximum offset of the comparator

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For the design a 10 bit sar adc , what should be the maximum offset of the comparator

Hi Guys,
Iam going to design a 10 bit cmos adc, using SAR architecture, with capacitif dac, my question is : what should be the maximum offset of the comparator, less than half lsb ?

Thanks in advance

Gump
 

how to find the sizing of the capacitance for a 10 bit sar adc

Hi Guys,

Regarding a 10 bit sar adc, using binary capacitance for the DAC

How to find the sizing capacitance of the unity capacitance, thermal noise KT/C and DNL

For my example, 1 LSB =1mv

If I consider 1/2 LSB, Ihave found a capacitance of 16.5fF, but how to check , if it's the correct value for the DNL ?

What is the hand calculation for the DNL ??

Thanks in advance
 

Re: how to find the sizing of the capacitance for a 10 bit sar adc

Assume the offset is linear/insignificant (with offset-cancellation), the linearity is limited by the matching of the DAC capacitors and the DAC type (binary-/themometer-code). Binary type has fewer switches but larger DNL; both types have the same INL.

 

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