Hi erikl:
I try to describe what I understand:
The thermal generation/recombination occurs everywhere in the semiconductor all the time.
For P-type sub, the electrons are attracted to the SiO2/Si interface by the positive VGB (NMOS), and the inversion layer between Drain and Source is formed. The capacitance is formed.(top plate is metal / bottom plate is inversion layer / dielectric is SiO2)
The difference increased speed of VGB will get the difference capacitance (difference C-V curve when VGB > Vth).
If I am wrong, please correct me.
mpig