For loop timing query

[nesta]

Hi VhdlExperts,

I would like to understand about how the timing is decided.

For example if i have a for loop inside a process which runs on every rising edge of the clock signal, Is it guaranteed that the for loop will complete within one clock cycle.

eg:
test: process(clk)
begin
if(clk ='1' and clk'event) then
for i in 0 to 100 loop
--- do somematrix multiplication.
end loop;

for i in 0 to 100 loop
--- do somematrix addition.
end loop;

end if;
end process;

Is the forloop guaranteed to complete within 1 clk cycle. Please explain.

Thanks.

 

[FvM]

Is it guaranteed that the for loop will complete within one clock cycle.

Yes, a HDL loop statement hasn't to do with sequence in time. It instructs to do something parallel.

 

[std_match]

Is the forloop guaranteed to complete within 1 clk cycle. Please explain.
Thanks.

Yes, but there is no guarantee for the clock frequency you can use if you try to run it in real hardware. The synthesis tool will tell you the maximum frequency.

If the result from one iteration in the loop is used in the next iteration, the resulting hardware will be a long chain of matrix hardware, and the maximum frequency will be very low.

In that case it is probably better to create a pipeline by putting registers between each stage. This means that the clock frequency can be higher. A new result will still be produced every clock cycle, but in the example there will be a delay of 101 clock cycles.

VHDL is not a programming language. It describes what the hardware does, but not how it is done. The synthesized hardware for the example will be completely different if the input data for one iteration does not depend on the previous iteration. It will be a parallel structure instead of a chain.

It is easy to write a few lines of code that will synthesize to hardware that will not fit even in the biggest FPGA.