For Loop in one clock cycle?

[eshbonzie]

Hey guys,

Im kinda new to VHDL and trying to implement an algorithm which does the follwoing:

it compares a pixel (8 bits) with 640(640*8bits = 5120 bits) other pixels, if a match is found a matching counter is incremented to count the number of matches.

I designed an entity for this as follows:

entity MatchingalgorithmModule is
Port ( Clk : in STD_LOGIC;
En : in STD_LOGIC;
FrameLine_Bitstream : in STD_LOGIC_VECTOR (5119 downto 0);
FrameLineNumber : in STD_LOGIC_VECTOR (8 downto 0);
CenterPixel : in STD_LOGIC_VECTOR (7 downto 0);
MatchesFound : out STD_LOGIC_VECTOR (13 downto 0));
end MatchingalgorithmModule;

architecture Behavioral of MatchingalgorithmModule is

signal MatchesFound_s : STD_LOGIC_Vector(13 downto 0);

begin

process(Clk)

variable matchCount_v : integer := 0;
variable index_v : integer := 5120;

begin

if(rising_edge(Clk)) then

for i in 1 to 640 loop

if(FrameLine_Bitstream((index_v-1) downto (index_v-8)) = CenterPixel) then

matchCount_v := matchCount_v + 1;

end if;

index_v := index_v - 8 ;

end loop;

index_v := 5120;

end if;

if(Clk'event and Clk = '1') then

MatchesFound_s <= conv_std_logic_vector(matchCount_v, 14);
matchCount_v := 0;

end if;

end process;

MatchesFound <= MatchesFound_s;

end Behavioral;

I wrote a textbench to generate random values for testing the entity as follows:

stim_proc: PROCESS

VARIABLE seed1, seed2 : positive; -- Seed values for random generator
VARIABLE rand : real; -- Random real-number value in range 0 to 1.0
VARIABLE int_rand : integer; -- Random integer value in range 0..4095
VARIABLE stim : std_logic_vector(1 DOWNTO 0); -- Random 12-bit stimulus

BEGIN


for test_case_index in 8 downto 1 loop

wait until rising_edge(Clk);
UNIFORM(seed1, seed2, rand); -- generate random number
int_rand := INTEGER(TRUNC(rand*4.0));
FrameLine_Bitstream((test_case_index*2)-1 downto test_case_index*2-2) <= std_logic_vector(to_unsigned(int_rand, stim'LENGTH)); -- convert to std_logic_vector
CenterPixel <= "00000000";

--wait for Clk_period*10;
end loop;

END PROCESS;

it generates a random two by two bits for the 5120 bit input vector. The results after simulating seemed to be ok, the only thing which I worry about is
that the number of matches found decreases by one every clock cycle. Before simulating I assumed that the number of matches found should change randomly from one clock cycle to the other.

I know that a for loop is executed in one clock cycle. However I'm still curious to get some explanation about this. Is it really possible to manipulate more than
5000 bits only in one clock cycle?..if yes, what are the limits to this? also what about the previous design does it seem to be ok or is there a fatal mistake that am missing?

Thanks,

Eshbon

 

[vipinlal]

some comments about the code you have written :
1)try to pass the bytes one by one rather than all the 640 bytes together.
2)try to avoid for loop in this case.Instead take each byte at a time per clock cycle and do the comparison. A for loop of this long will give you a head ache during synthesis.

About the bug you are facing here:
Did you see the output by changing the seed values? May be you have used the same seed values each time you tested it.

 

[TrickyDicky]

VHDL is not a programming language. For loops do not "Execute", they equate to a logic circuit. You have basically created 640 chained logic circuits with that loop. So yes you can complete it in one clock cycle, if your clock is running really really slowly (like a few KHz max!).

Forget about "executing" code, try thinking about the circuit before writing any code. Remember, this is hardware DESCRIPTION language, not hardware programming language.

 

[eshbonzie]

Thank you guys, I appreciate your help...I guess now after what you said I know what to do.

Cheers!