I guess the poster is trying to do a number of sequential operations iteratively. A simple for loop as described above is useless in such a case, since all the operations are performed concurrently in HDLs. Use State Machines for such a case.
firstly, I must say, "for loop" is not for fpga directly, it's for the synthesis tools actually. It's just a combintional logic statement. the synthesis tools will calculte the logic equation's result and map it to gates!
look up in the synthesis software's manual.
I don't understand the question. A FOR loop itself is not synthesizable.
Synthesizes means hardware translation. Hardware can result using some other statements with the FOR loop such as GENERATE. You need FOR in conjunction with other statements/function to develop a synthesized circuit.
A for loop can be synthesized if and only if its parameters are Constants, else it can't be synthesized, you can instead use an FSM, which of course will introduce a delay but you may pipeline the design, or else you may use an asynchronous FSM which is highly indesirable in FPGA designs mainly because the routing delays are not predictable, so an FSM and a pipeline can do what ever you want do.
Loops are synthesable
if constraints are static variables
and functions in the loop are synthesable,
and the synthesized netlist fit the FPGA resources.
Each iteration is mapped in its own resource.
That means that the loop is fully unrolled and than synthesized.
Therefore the loop I from 1 to 100
with the body X*Y gives 100 parallel multipliers.
Sometimes loops are very useful.
For example searching in the loop for the leading 1 in the vector
gives exellent parity check unit.
You can use FOR in HDL at any target level (Fpga, Asic). But you have to not do somethings.
1- Don't use break or exit in for.
2- Don't use variable length loop.
3- Don't use complex loops. for example "for ( if () . if () )". (it's always not good solution but sometimes synthesizable).
4- Try to use "generate" statements instead of "for loop".