pinkyvidya
Member level 2
error 10170 in verilog
is it possible to write for loop in always block in verilog???
the piece of code i tried is given below...
always @(posedge clk)
begin
a=1'b0;
l=1'b0;
yout(l)=8'b0;
for(j=0;j<=3;j=j+1)
begin
b=1'b0;
for(i=0;i<=3;i=i+1)
begin
for(k=0;k<=3;k=k+1)
begin
n=a;
m=b;
z=xin
n=n+1;
m=m+4;
yout(l)=yout(l)+z;
l=l+1;
end
b=b+1;
end
a=a+1;
end
end
this is showing error like
"Error (10170): Verilog HDL syntax error at matmul.v(17) near text "="; expecting ";" "
"Error (10170): Verilog HDL syntax error at matmul.v(30) near text "="; expecting ";" "
v(17) is yout(l)=8'b0;
v(30) is yout(l)=yout(l)+z;
kindly anyone clarify my doubt....iwill be very thankful
is it possible to write for loop in always block in verilog???
the piece of code i tried is given below...
always @(posedge clk)
begin
a=1'b0;
l=1'b0;
yout(l)=8'b0;
for(j=0;j<=3;j=j+1)
begin
b=1'b0;
for(i=0;i<=3;i=i+1)
begin
for(k=0;k<=3;k=k+1)
begin
n=a;
m=b;
z=xin
n=n+1;
m=m+4;
yout(l)=yout(l)+z;
l=l+1;
end
b=b+1;
end
a=a+1;
end
end
this is showing error like
"Error (10170): Verilog HDL syntax error at matmul.v(17) near text "="; expecting ";" "
"Error (10170): Verilog HDL syntax error at matmul.v(30) near text "="; expecting ";" "
v(17) is yout(l)=8'b0;
v(30) is yout(l)=yout(l)+z;
kindly anyone clarify my doubt....iwill be very thankful