For Loop and Synthesis Behaviour...plz guide.

[Mirzaaur]

hi all,

if I am having two nested for loops just to fill in 64*64 one bit matrix.
in simulation data is shifted in one clock cycle. but how it will behave once its synthesized. how many clock cycles it will take to write the matrix from memory.
Memory can be considered on chip ....!:!:

thanks in advance,

mirza

 

[echo47]

What language are you are using? Can you show us your code?

 

[Mirzaaur]

Thanks for your reply:-
I am using VHDL

.......--------------
if (I<=64) then

for R in 0 to 63 loop
for C in 0 to 63 loop
Block(R,C) <= int_to_bv(data_in);

wait until s_clk = '1';
end loop;
wait until s_clk = '1';
I := I+1;
end loop;

----------------------------------------------------------
thank you very much for your time.

mirza